1. Field of the Invention
The invention relates generally to micro-electronic circuitry. More specifically, the invention relates to a method for synchronizing clock and data signals.
2. Background Art
A clock signal is critical to the operation of a microprocessor based computer system. The clock signal initiates and synchronizes the operation of almost all of the components of such a computer system. FIG. 1 shows a prior art overview of a clock distribution system. The computer system 10 broadly includes an input/output (“IO”) ring 12 that is part of the microprocessor chip and surrounds the “core” 14 of the system. The system clock signal 16 is fed through the IO ring 12 to a phased locked loop (“PLL”) 15 inside the core 14. A PLL is a component that uses feedback to maintain an output signal in a specific phase or frequency relationship with an input signal. In the case of a computer system, a PLL is used to synchronize the microprocessor (“chip”) clock with the external (“system”) clock. The PLL 15, after synchronizing the system clock signal with the chip clock signal, feeds it to a global clocking grid 18 for the chip. The global clocking grid 18 feeds the signal data/scan paths 30 and 32 and various components such as system latches 22, local clocking grids 20, and a feed back loop 26 that returns to the PLL 15. The local clocking grids 20 feed the base components of the core 14 such as flip-flops 24 which are basic data storage devices.
The end product of the system 10 is the output data 34 during normal operation or scan out data 36 in the case of a scanning test sequence. Each of these system outputs 34 and 36 passes through a clocked storage device 38 and 40 in the I/O ring 12. Since the clock signal in the I/O ring 37 is generally much slower than the clock signal in the core 14, a need exists to synchronize the data 34 from the core 14 with the system clock signal 16.